Laminated Inverter Busbars: Parasitic Inductance Reduction Principle and Key Considerations for High Current Design

The core advantage of the Laminated Copper Bar stems from its "sandwich" laminated structure-positive and negative conductive copper layers are tightly stacked together through an insulating medium (such as polyimide or epoxy resin), forming conductive loops with opposite current directions and overlapping spatial positions. When a high-frequency, high-current flows through, the current in the positive and negative copper layers generates magnetic fields of equal magnitude but opposite direction. These magnetic fields cancel each other out, significantly weakening the total magnetic flux linkage of the loop and thus significantly reducing parasitic inductance. Actual measurement data shows that a 200mm long, 100mm wide, and 0.5mm thick Laminated Copper BusBar can control its parasitic inductance to 3-5nH, while the parasitic inductance of a parallel busbar of the same size can reach as high as 110nH, a difference of over 20 times. This low inductance characteristic not only suppresses voltage spikes but also reduces switching losses, lowers electromagnetic interference (EMI), and improves the overall system efficiency and reliability.

The design of Laminated Bus Bars for Telecom requires attention to four core elements: First, the positive and negative copper layers must be strictly parallel and overlapping to maximize the overlap area of ​​the current path and minimize the remaining loop area; second, the insulation layer thickness should be minimized as much as possible, theoretically, the smaller the spacing, the more significant the magnetic field cancellation effect; third, the width of the Laminated Bus Bar needs to be reasonably designed, as a wider copper layer can enhance the uniformity of current distribution under the high-frequency skin effect and further suppress inductance; fourth, the mounting hole positions need to be symmetrically arranged to ensure that the connection distance between power devices (such as IGBTs) and DC support capacitors is minimized, reducing additional loop inductance. In addition, Laminated Inverter Busbars also have advantages such as high current carrying capacity (3-5A/mm² per unit cross-sectional area), high heat dissipation efficiency (multi-layer thin copper structure increases heat dissipation area), and compact structure (integrated design replaces scattered cables), and are widely used in high-current scenarios such as new energy vehicle inverters, photovoltaic energy storage converters, industrial frequency converters, and rail transit traction systems.

Quantifying parasitic inductance requires a double-pulse test, which is an industry-standard testing method. During testing, a half-bridge circuit needs to be constructed. A double-pulse signal is applied through the low-side switch, and the collector-emitter voltage (Vce) and current waveforms of the upper-arm device (such as an IGBT) are measured. It is important to select the turn-on transient (rather than the turn-off transient) for measurement, as the current change is more stable at turn-on, avoiding interference from the reverse recovery current of the freewheeling diode. According to the formula L = ΔVce / (di/dt), the total parasitic inductance of the loop can be calculated by reading the voltage spike (ΔVce) and current change rate (di/dt) at the turn-on instant. In actual measurements, the parasitic inductance of the loop using laminated busbar connectors is typically around 75nH, while that of traditional parallel busbars exceeds 200nH, verifying the significant advantages of the laminated structure.

When selecting a power supply, the appropriate solution must be chosen based on the current rating: For applications below 100A, conventional Laminated Busbar Power Solutions with an insulation layer thickness of 0.2-0.3mm can be used; for 100-500A applications, a thicker copper layer and an insulation layer thickness of 0.3-0.5mm are required; for 500-1000A applications, a multi-layer stacked structure with an insulation layer thickness of 0.5mm is necessary; and for applications above 1000A, a custom design is required, with current distribution and short-circuit strength optimized through simulation. The design process must adhere to the principle of minimizing the current loop area, while also considering heat dissipation requirements and mechanical strength. For high-voltage applications, the insulation withstand voltage rating must also be verified.